added IPA to complete the formation of names of parallelization regions
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@@ -1264,6 +1264,8 @@ static bool runAnalysis(SgProject &project, const int curr_regime, const bool ne
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moveAllocatesInterproc(arrayLinksByFuncCalls);
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propagateRegionInfo(declaredArrays, arrayLinksByFuncCalls, subs_parallelRegions);
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removeDistrStateFromDeadFunctions(allFuncInfo, declaredArrays);
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propagateArrayFlags(arrayLinksByFuncCalls, declaredArrays, SPF_messages);
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}
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@@ -1681,30 +1683,11 @@ static bool runAnalysis(SgProject &project, const int curr_regime, const bool ne
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findDeadFunctionsAndFillCalls(allFuncInfo_IR, SPF_messages, true);
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else if (curr_regime == GET_ALL_ARRAY_DECL)
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{
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bool hasNonDefaultReg = false;
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for (auto &elem : subs_parallelRegions)
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if (elem->GetName() != "DEFAULT")
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hasNonDefaultReg = true;
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if (hasNonDefaultReg)
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if (ignoreArrayDistributeState)
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{
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for (auto array : declaredArrays)
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{
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if (array.second.first->GetRegionsName().size() == 0)
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array.second.first->SetDistributeFlag(DIST::NO_DISTR);
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else if (array.second.first->GetRegionsName().size() == 1)
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{
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string regName = *array.second.first->GetRegionsName().begin();
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convertToLower(regName);
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if (regName == "default")
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array.second.first->SetDistributeFlag(DIST::NO_DISTR);
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}
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}
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}
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if (ignoreArrayDistributeState)
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for (auto array : declaredArrays)
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array.second.first->SetDistributeFlag(DIST::NO_DISTR);
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}
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}
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else if (curr_regime == GCOV_PARSER)
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{
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